The present invention relates to a method and/or architecture for a package integrating multiple chips generally and, more particularly, to a package having multiple programmable logic devices interconnected with each other.
A design cycle for a newer and larger complex programmable logic device (CPLD) can require several months to complete. Considerable resources must be spent in design, simulations, and test cycles for the new CPLD prior to producing a working prototype in silicon. After the working prototypes are available, additional resources can be expended for additional testing.
While the new CPLD is being developed, customers must use multiple existing CPLD devices to meet design requirements for a number of gates greater than in an individual CPLD device. Using multiple CPLD devices requires additional time and effort to segregate functionality among the CPLD devices, program the individual CPLD devices, and assemble the individual CPLD devices onto the boards. Multiple CPLD devices can consume greater power and require more board space that a single CPLD device.
The present invention concerns a device having two or more programmable logic devices within an assembly apparatus. A first programmable logic device may be configured to have (i) a first signal interface and (ii) a second signal interface. A second programmable logic device may be configured to have (i) a third signal interface and (ii) a fourth signal interface. The assembly apparatus is generally configured to (i) mount the first programmable logic device and (ii) mount the second programmable logic device. A first external contact may be connected to the first signal interface. A second external contact may be connected to the fourth signal interface. A direct connection may be provided between the second signal interface and the third signal interface.
The objects, features and advantages of the present invention include providing a package having multiple programmable logic devices that may provide for (i) a high gate density, (ii) inter-PLD communications within the package, and/or (iii) external access to the inter-PLD communications.